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| STM32F756VG Datasheet, PDF (184/228 Pages) STMicroelectronics – Up to 25 communication interfaces | |||
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Electrical characteristics
STM32F756xx
Table 99. Synchronous non-multiplexed PSRAM write timings(1)
Symbol
Parameter
Min
Max
t(CLK)
FMC_CLK period
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0â¦2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16â¦25)
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16â¦25)
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1. Guaranteed by characterization results.
2THCLKâ1
-
-
2.5
THCLK+0.5
-
-
1.5
0
-
-
2.5
0
-
-
1.5
THCLK+1
-
-
3
1.5
-
THCLK+0.5
-
2
-
3.5
-
Unit
ns
NAND controller waveforms and timings
Figure 66 through Figure 69 represent synchronous waveforms, and Table 100 and
Table 101 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
⢠COM.FMC_SetupTime = 0x01;
⢠COM.FMC_WaitSetupTime = 0x03;
⢠COM.FMC_HoldSetupTime = 0x02;
⢠COM.FMC_HiZSetupTime = 0x01;
⢠ATT.FMC_SetupTime = 0x01;
⢠ATT.FMC_WaitSetupTime = 0x03;
⢠ATT.FMC_HoldSetupTime = 0x02;
⢠ATT.FMC_HiZSetupTime = 0x01;
⢠Bank = FMC_Bank_NAND;
⢠MemoryDataWidth = FMC_MemoryDataWidth_16b;
⢠ECC = FMC_ECC_Enable;
⢠ECCPageSize = FMC_ECCPageSize_512Bytes;
⢠TCLRSetupTime = 0;
⢠TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
184/228
DocID027589 Rev 4
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