STM32F756VG Datasheet, PDF (140/228 Pages) STMicroelectronics – Up to 25 communication interfaces

Electrical characteristics
STM32F756xx
Table 56. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
FT, TTa and NRST I/O input
high level voltage⁽⁵⁾
1.7 V≤V_DD≤3.6 V
0.45V_DD+0.3⁽¹⁾
0.7V_DD(2)
-
V_IH
BOOT I/O input high level
voltage
1.75 V≤V_DD ≤3.6 V, –
40 °C≤T_A ≤105 °C
1.7 V≤V_DD ≤3.6 V,
0.17V_DD+0.7⁽¹⁾
-
0 °C≤T_A ≤105 °C
FT, TTa and NRST I/O input
hysteresis
1.7 V≤V_DD≤3.6 V
10%V_DD(3)
-
V_HYS
BOOT I/O input hysteresis
1.75 V≤V_DD ≤3.6 V, –
40 °C≤T_A ≤105 °C
0.1
-
1.7 V≤V_DD ≤3.6 V,
0 °C≤T_A ≤105 °C
I/O input leakage current ⁽⁴⁾
V_SS ≤V_IN ≤V_DD
-
-
I_{lkg I/O FT input leakage current}
(5)
V_IN = 5 V
-
-
Max
Unit
-
V
-
-
V
-
±1
µA
3
All pins
except for
PA10/PB12
(OTG_FS_ID
Weak pull-up _{,OTG_HS_ID}
R_PU
equivalent
resistor⁽⁶⁾
)
PA10/PB12
(OTG_FS_ID
,OTG_HS_ID
)
Weak pull-
R_PD
down
equivalent
resistor⁽⁷⁾
All pins
except for
PA10/PB12
(OTG_FS_ID
,OTG_HS_ID
)
PA10/PB12
(OTG_FS_ID
,OTG_HS_ID
)
V_IN = V_SS
V_IN = V_DD
30
40
50
7
10
14
kΩ
30
40
50
7
10
14
C_IO(8) I/O pin capacitance
-
-
5
-
pF
1. Guaranteed by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 55: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 55: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
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