STM32F756VG Datasheet, PDF (160/228 Pages) STMicroelectronics – Up to 25 communication interfaces

Electrical characteristics
STM32F756xx
Refer to Section 5.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Table 77. I²S dynamic characteristics⁽¹⁾
Symbol
Parameter
Conditions
Min
f_MCK
f_CK
I2S Main clock output
I2S clock frequency
-
Master data: 32 bits
Slave data: 32 bits
D_CK
t_v(WS)
t_h(WS)
t_su(WS)
I2S clock frequency duty cycle Slave receiver
WS valid time
Master mode
WS hold time
Master mode
WS setup time
Slave mode
Slave mode
PCM short pulse mode⁽³⁾
t_h(WS)
WS hold time
Slave mode
Slave mode
PCM short pulse mode⁽³⁾
t_{su(SD_MR)}
t_{su(SD_SR)}
t_{h(SD_MR)}
t_{h(SD_SR)}
t_{v(SD_ST)}
t_{v(SD_MT)}
t_{h(SD_ST)}
t_{h(SD_MT)}
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
1. Guaranteed by characterization results.
2. The maximum value of 256xFs is 45 MHz (APB1 maximum frequency).
3. Measurement done with respect to I2S_CK rising edge.
256x8K
-
-
30
-
0
5
3
0
2
5
1
5
1.5
-
-
5
0
Max
256xFs⁽²⁾
64xFs
64xFs
70
5
-
-
-
-
-
-
-
-
-
16
3.5
-
-
Unit
MHz
MHz
%
ns
ns
Note:
Refer to RM0385 reference manual I2S section for more details on the sampling frequency
(F_S).
f_MCK, f_CK, and D_CK values reflect only the digital peripheral behavior. The values of these
parameters might be slightly impacted by the source clock precision. D_CK depends mainly
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F_S
maximum value is supported for each mode/condition.
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