STCD1020_10 Datasheet, PDF (18/40 Pages) STMicroelectronics – Multichannel clock distribution circuit

DC and AC parameters
STCD1020, STCD1030, STCD1040
Table 9.
Symbol
DC and AC characteristics (2.8 V supply) (continued)
Parameter
Condition⁽¹⁾
Min
Typ Max Unit
1 channel enabled
1.8
I_ACT Active current⁽⁵⁾
2 channels enabled
3 channels enabled
2.3
mA
2.85
4 channels enabled
3.4
I_SB Standby current
R_IN Input resistance
C_IN Input capacitance
t_r/f
Rise/fall times⁽⁶⁾
All buffers disabled
At DC level
f = 26 MHz
Vin = 1Vpp, C_L = 10 pF
Square wave input/output
1 μA
>100
kΩ
3
4 pF
2
5 ns
BW Signal bandwidth⁽³⁾
V_ENH
V_ENL
Enable voltage high⁽⁷⁾
Enable voltage low⁽⁷⁾
P_N
Additive phase noise⁽³⁾⁽⁸⁾
Vin =1 Vpp, -1dB, C_L = 10 pF
Sine wave input/output
EN1~EN4
1.2
EN1~EN4
at 1 kHz offset
at 10 kHz offset
at 100 kHz offset
52
–135
–145
–150
MHz
V
0.6 V
dBc/
Hz
t_RECB
t_RECC
Buffer recovery time from off to on
STCD10x0 active recovery time
from standby to active
STCD10x0 active
20
µs
50
µs
C_L Capacitive load for each channel
10
20 pF
R_L Resistive load for each channel
10
kΩ
1. Valid for ambient operating temperature: T_A = –40 °C to 85 °C; V_CC = 2.5 V to 3.6 V; typical T_A = 25 °C;
Load capacitance = 10 pF (except where noted).
2. Clock input voltage level should not exceed supply rails.
3. Simulated and determined via design and NOT 100% tested.
4. The quiescent current is measured when the enable pins are active, but without input master clock signal (f_MCLK = 0 Hz).
5. The active current is dependent on the master clock input Vpp and frequency and the capacitive load condition. The typical
test condition is 26 MHz sine wave with 1 Vpp master clock input, C_L = 10 pF.
6. The rise time is measured when clock edge transfers from 10% V_CC to 90% V_CC. The fall time is measured when clock
edge transfers from 90% V_CC to 10% V_CC.
7. Other test results are under test condition V_ENH = 1.8 V and V_ENL = 0 V.
8. Guaranteed with the supply noise of 30 µ Vrms from 300 Hz to 50 kHz.
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Doc ID 13823 Rev 6