STCD1020_10 Datasheet, PDF (13/40 Pages) STMicroelectronics – Multichannel clock distribution circuit

STCD1020, STCD1030, STCD1040
Application information
Figure 8. Typical application circuit using STCD1040 for baseband peripherals in
mobile phone
VCC
BT_External_Req
VCTCXO
VCC
STCD1040 ^EN4
CLK4
MCLK
EN3
CLK3
EN2
CLK2
EN1
CLK1
GND
Bluetooth
WLAN
GPS
Other
device
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4.2
Connection of the source clock to MCLK
If the output of the clock source voltage level is within the supply rails of the STCD1020,
STCD1030 and STCD1040, the output of the source clock should be connected directly to
the MCLK of the clock distribution circuits. This is described in Figure 9. The direct
connection of the source clock is the common case and a DC-CUT capacitor is saved on
PCB.
Figure 9. Direct connection of the source clock
VCC
Note:
OUT
VCTCXO
MCLK
STCD1020
STCD1030
STCD1040
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The input clock voltage level of the STCD1020, STCD1030, and STCD1040 cannot exceed
the supply rails when it is directly connected to the source clock. If it is needed to connect a
source clock with the voltage level exceeds the supply rails of the clock distribution circuits,
the user needs to connect a DC-CUT capacitor serially as shown in Figure 10. A voltage
divider formed by a resistor string is also needed to set a proper DC bias for the clock input
Doc ID 13823 Rev 6
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