STM32F437XX Datasheet, PDF (175/240 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera&LCD-TFT

STM32F437xx and STM32F439xx
Electrical characteristics
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms
TW.%
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-36
Table 92. Asynchronous multiplexed PSRAM/NOR write timings⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max
Unit
t_w(NE)
FMC_NE low time
t_{v(NWE_NE)} FMC_NEx low to FMC_NWE low
t_w(NWE)
FMC_NWE low time
t_{h(NE_NWE)} FMC_NWE high to FMC_NE high hold time
t_{v(A_NE)}
FMC_NEx low to FMC_A valid
t_{v(NADV_NE)} FMC_NEx low to FMC_NADV low
t_w(NADV)
FMC_NADV low time
t_{h(AD_NADV)} FMC_AD(adress) valid hold time after FMC_NADV high)
t_{h(A_NWE)} Address hold time after FMC_NWE high
t_{h(BL_NWE)} FMC_BL hold time after FMC_NWE high
t_{v(BL_NE)}
FMC_NEx low to FMC_BL valid
t_{v(Data_NADV)} FMC_NADV high to Data valid
t_{h(Data_NWE)} Data hold time after FMC_NWE high
1. C_L = 30 pF.
2. Guaranteed by characterization results.
4T_HCLK 4T_HCLK+0.5 ns
T_HCLK − 1 T_HCLK+0.5 ns
2T_HCLK 2T_HCLK+0.5 ns
T_HCLK
-
ns
-
0
ns
0.5
1
ns
T_HCLK − 0.5 T_HCLK+ 0.5 ns
T_HCLK − 2
-
ns
T_HCLK
-
ns
T_HCLK − 2
-
ns
-
2
ns
-
T_HCLK +1.5 ns
T_HCLK +0.5
-
ns
DocID024244 Rev 10
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