STM32F437XX Datasheet, PDF (159/240 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera&LCD-TFT

STM32F437xx and STM32F439xx
Electrical characteristics
Symbol
Table 74. ADC characteristics (continued)
Parameter
Conditions
Min
Typ
Max Unit
12-bit resolution
Single ADC
-
Sampling rate
f_S(2) (f_ADC = 30 MHz, and
t_S = 3 ADC cycles)
12-bit resolution
Interleave Dual ADC
-
mode
12-bit resolution
Interleave Triple ADC
-
mode
I_VREF+(2)
ADC V_REF DC current
consumption in conversion
-
mode
I_VDDA(2)
ADC V_DDA DC current
consumption in conversion
-
mode
-
2
Msps
-
3.75 Msps
-
6
Msps
300
500
µA
1.6
1.8
mA
1. V_InDteDrAnam_l i_rn_eim_seu_tm_OFva_Fl)u.e of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:
2. Guaranteed by characterization results.
3. V_REF+ is internally connected to V_DDA and V_REF- is internally connected to V_SSA.
4. R_ADC maximum value is given for V_DD=1.7 V, and minimum value for V_DD=3.3 V.
5. For external triggers, a delay of 1/f_PCLK2 must be added to the latency specified in Table 74.
Equation 1: R_AIN max formula
R_AIN
=
--------------------⁽--^k------^–-----⁰----^.--⁵-----⁾--------------------
f_ADC × C_ADC × ln (2^{N + 2})
–
R_ADC
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
Symbol
Table 75. ADC static accuracy at f_ADC = 18 MHz
Parameter
Test conditions
Typ
Max⁽¹⁾
Unit
ET Total unadjusted error
±3
EO Offset error
EG Gain error
f_ADC =18 MHz
V_DDA = 1.7 to 3.6 V
±2
V_REF = 1.7 to 3.6 V
±1
ED Differential linearity error
V_DDA −V_REF < 1.2 V
±1
EL Integral linearity error
±2
1. Guaranteed by characterization results.
±4
±3
±3
LSB
±2
±3
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