STM32F446XC Datasheet, PDF (171/202 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 225DMIPS, up to 512kB Flash/128+4KB RAM, USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces

STM32F446xC/E
Electrical characteristics
Figure 63. SDRAM write access waveforms
&-#?3$#,+
TD3$#,+,?!DD2
&-#?!>@
2OWN
TD3$#,+,?!DD#
TH3$#,+,?!DD2
#OL
#OL #OLI
#OLN
TD3$#,+,?3.$%
TH3$#,+,?!DD#
TH3$#,+,?3.$%
&-#?3$.%;=
TD3$#,+,?.2!3
TH3$#,+,?.2!3
&-#?3$.2!3
&-#?3$.#!3
TD3$#,+,?.#!3
TD3$#,+,?.7%
TH3$#,+,?.#!3
TH3$#,+,?.7%
&-#?3$.7%
TD3$#,+,?$ATA
&-#?$;=
TD3$#,+,?.",
&-#?.",;=
$ATA
$ATA $ATAI $ATAN
TH3$#,+,?$ATA
Table 102. SDRAM write timings⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max
F_(SDCLK)
t_w(SDCLK)
t_{d(SDCLKL _Data)}
t_{h(SDCLKL _Data)}
t_{d(SDCLK _Add)}
t_{d(SDCLKL _SDNWE))}
t_{h(SDCLKL_SDNWE))}
t_{d(SDCLKL_SDNE))}
t_{h(SDCLKL_SDNE)}
t_{d(SDCLKL_SDNRAS)}
t_{h(SDCLKL_SDNRAS)}
t_{d(SDCLKL_SDNCAS)}
t_{h(SDCLKL_SDNCAS)}
Frequency of operation
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
Chip select valid time
Chip select hold time
SDNRAS valie time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
-
2T_HCLK - 0.5
-
0.5
-
-
0
-
0
-
0
-
0
90
2T_HCLK + 0.5
2
-
3
1.5
-
1.5
-
1
-
1
-
1. C_L = 10 pF on data and address line. C_L=15 pF on FMC_SDCLK.
2. Guaranteed based on test during characterization.
-36
Unit
MHz
ns
DocID027107 Rev 6
171/202
175