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| STM32F446XC Datasheet, PDF (130/202 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 225DMIPS, up to 512kB Flash/128+4KB RAM, USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces | |||
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Electrical characteristics
STM32F446xC/E
Table 63. SPI dynamic characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode, SPI presc = 2
TPCLK - 1.5 TPCLK TPCLK + 1.5
tsu(NSS) NSS setup time
Slave mode, SPI presc = 2
4TPCLK
-
-
th(NSS) NSS hold time
Slave mode, SPI presc = 2
2TPCLK
tsu(MI)
tsu(SI)
Data input setup time
Master mode
Slave mode
4
-
-
3
-
-
th(MI)
th(SI)
Data input hold time
Master mode
Slave mode
4
-
-
2
-
-
ta(SO) Data output access time Slave mode
7
-
21
ns
tdis(SO) Data output disable time Slave mode
5
-
12
tv(SO)
Data output valid/hold
time
Slave mode (after enable edge),
2.7V ⤠VDD ⤠3.6V
Slave mode (after enable edge),
1.7 V ⤠VDD ⤠3.6 V
-
-
7.5
22
7.5
10.5
th(SO)
Data output valid/hold
time
Slave mode (after enable edge)
5
-
-
tv(MO) Data output valid time Master mode (after enable edge)
-
1.5
5
th(MO) Data output hold time Master mode (after enable edge)
0
-
-
1. Guaranteed based on test during characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
Figure 36. SPI timing diagram - slave mode and CPHA = 0
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130/202
DocID027107 Rev 6
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