AN966 Datasheet, PDF (16/21 Pages) STMicroelectronics – The front-end stage of conventional off-line converters

AN966 APPLICATION NOTE
Assuming an lgap/le ratio of 2.5%
Considering the E series, the E25
the minimum core size estimate gives a minimum
(2.99 cm³ effective volume) has been selected.
volume
of
2.6
cm³.
To reduce copper losses, a multiple wire (20 x 0.1mm) has been adopted. The resistance of the winding
is about 0.75Ω at 35 kHz , so the maximum copper losses are about 1W.
OUTPUT FILTER CAPACITOR (C6):
The specification on the output voltage ripple determines the capacitance value.
Assuming 50 Hz minimum line frequency, a 47µF/450V capacitor has been selected. This gives an out-
put ripple ∆Vo = ±7 V.
MULTIPLIER SETTING (R1, R2, R3) AND SENSE RESISTOR (R9, R10):
The multiplier divider is selected so to exploit about 80% of its linear dynamics (VMULTpkx = 2.5V) as per
the procedure described in pin 3 description. The sense resistor is then determined.
As to R9 and R10, metal film resistors are suitable because of the high peak current flowing in it.
OUTPUT DIVIDER (R11, R12, R13):
R11 + R12 is selected so to achieve the desired overvoltage trip level (∆VOVP = 60V), while R13 is cho-
sen so to get the specified output regulated voltage.
ERROR AMPLIFIER COMPENSATION
The error amplifier has been compensated so as to get a type 2 amplifier that provides a pole at the ori-
gin and a zero-pole pair. As compared to a type1 amplifier (compensated with a single capacitor) this
compensation offers a higher phase margin under all operating conditions and is therefore recom-
mended when the PFC pre-regulator powers a DC-DC converter. However, the twice-mains-frequency
gain will be higher because of the zero, which causes a higher ripple at the output of the E/A and, as a
result, a higher 3rd harmonic (and a higher THD) of the current drawn from the mains.
THD REDUCER
In the PCB there is provision for a network (see schematic of figure 13, in the dotted box) able to reduce
the crossover distortion of the PFC input current, that is the small flat region appearing at the zero cross-
ings of the mains voltage. The effect of this circuit is to force the ON-time of the power switch to increase
nearby the zero-crossings. As a result, the energy inside the boost inductor will be greater and the dead-
time during which there is no energy transfer is reduced. The circuit fine-tuning has to be made experi-
mentally.
NTC
The NTC has been moved from the input to the output, in series with the boost diode. In this way,
though still doing its job of inrush current limiter, it will undergo the output current instead of the input
current, as in the typical position, with a considerable power dissipation reduction. The extra voltage on
mosfet’s drain while the boost diode is conducting is negligible.
The schematic circuit of fig. 13 shows the values of all the parts used. In fig. 14 the printed circuit board
and the component layout of the demonstration board are shown.
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