STM32F303RD Datasheet, PDF (156/184 Pages) STMicroelectronics – Reset and supply management

Electrical characteristics
STM32F303xD STM32F303xE
Table 85. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min Typ
Max
Unit
Max frequency for a correct
Update rate⁽³⁾
DAC_OUT change when
small variation in the input
C_LOAD ≤50 pF,
R_LOAD ≥ 5 kΩ
code (from code i to i+1LSB)
t_WAKEUP(3)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
C_LOAD ≤50 pF,
R_LOAD ≥ 5 kΩ
PSRR+ ⁽¹⁾
Power supply rejection ratio
(to V_DDA) (static DC
measurement
C_LOAD = 50 pF,
No R_LOAD ≥ 5 kΩ,
-
-
1
MS/s
-
6.5
10
µs
-
–67
–40
dB
1. Guaranteed by design, not tested in production.
2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is
involved.
3. Data based on characterization results, not tested in production.
Figure 52. 12-bit buffered /non-buffered DAC
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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.21 Comparator characteristics
Table 86. Comparator characteristics⁽¹⁾
Symbol
Parameter
Conditions
Min.
Typ.
Max. Unit
V_DDA Analog supply voltage
-
V_IN
Comparator input voltage
range
-
V_BG
Scaler input voltage
-
V_SC
Scaler offset voltage
-
t_{S_SC}
Scaler startup time from
power down
-
2
-
3.6
0
-
V_DDA
V
-
V_REFINIT
-
-
±5
±10 mV
-
-
0.2
ms
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