M34E04B Datasheet, PDF (14/35 Pages) STMicroelectronics – 4-Kbit Serial Presence Detect EEPROM compatible

Device operation
M34E04B
3.6.3
Minimizing system delays by polling on ACK
The sequence, as shown in Figure 6, is:
• Initial condition: a Write cycle is in progress.
• Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
• Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 6. Write cycle polling flowchart using ACK
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During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t_w) is
shown in Table 13, but the typical time is shorter. To make use of this, a polling sequence
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