M34E04B Datasheet, PDF (11/35 Pages) STMicroelectronics – 4-Kbit Serial Presence Detect EEPROM compatible

M34E04B
3
Device operation
Device operation
The device supports the I²C protocol. This is summarized in Figure 4. Any device that sends
data onto the bus is defined to be a transmitter, and any device that reads the data is
defined to be a receiver. The device that controls the data transfer is known as the bus
master, and the other device is known as the slave device. A data transfer can only be
initiated by the bus master, which will also provide the serial clock for synchronization. The
memory device is always a slave in all communication.
3.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
3.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master. A Read command that is followed by NoAck can be followed by a Stop condition to
force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal EEPROM Write cycle.
3.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether a bus master or a slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9^th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
3.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
3.5
Memory addressing
To start a communication between the bus master and the slave device, the bus master
must initiate a Start condition. Following this, the bus master sends the device select code,
shown in Table 2 (on Serial Data (SDA), most significant bit first).
The Device Type Identifier Code (DTIC) consists of a 4-bit device type identifier, and a 3-bit
slave address (SA2, SA1, SA0). To address the memory array, the 4-bit device type
identifier is 1010b; to access the write-protection settings, it is 0110b.
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