M50FLW040A_06 Datasheet, PDF (13/64 Pages) STMicroelectronics – 4-Mbit (5 × 64 Kbyte blocks + 3 × 16 × 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory

M50FLW040A, M50FLW040B
2
Signal descriptions
Signal descriptions
There are two distinct bus interfaces available on this device. The active interface is selected
before power-up, or during Reset, using the Interface Configuration Pin, IC.
The signals for each interface are discussed in the Firmware Hub/low-pin count (FWH/LPC)
signal descriptions section and the Address/Address Multiplexed (A/A Mux) signal
descriptions section, respectively, while the supply signals are discussed in the Supply
signal descriptions section.
2.1
2.1.1
2.1.2
2.1.3
Firmware Hub/low-pin count (FWH/LPC) signal descriptions
Please see Figure 1 and Table 1.
Input/Output communications (FWH0/LAD0-FWH3/LAD3)
All Input and Output Communications with the memory take place on these pins. Addresses
and Data for Bus Read and Bus Write operations are encoded on these pins.
Input communication frame (FWH4/LFRAME)
The Input Communication Frame (FWH4/LFRAME) signal indicates the start of a bus
operation. When Input Communication Frame is Low, V_IL, on the rising edge of the Clock, a
new bus operation is initiated. If Input Communication Frame is Low, V_IL, during a bus
operation then the operation is aborted. When Input Communication Frame is High, V_IH, the
current bus operation is either proceeding or the bus is idle.
Identification inputs (ID0-ID3)
Up to 16 memories can be addressed on a bus, in the Firmware Hub (FWH) mode. The
Identification Inputs allow each device to be given a unique 4-bit address. A ‘0’ is signified
on a pin by driving it Low, V_IL, or leaving it floating (since there is an internal pull-down
resistor, with a value of R_IL). A ‘1’ is signified on a pin by driving it High, V_IH (and there will
be a leakage current of I_LI2 through the pin).
By convention, the boot memory must have address ‘0000’, and all additional memories are
given addresses, allocated sequentially, from ‘0001’.
In the Low Pin Count (LPC) mode, the identification Inputs (ID0-ID2) can address up to 8
memories on a bus. In the LPC mode, the ID3 pin is Reserved for Future Use (RFU). The
value on address A19-A21 is compared to the hardware strapping on the ID0-ID2 pins to
select the memory that is being addressed. For an address bit to be ‘1’, the corresponding
ID pin can be left floating or driven Low, V_IL (again, with the internal pull-down resistor, with
a value of R_IL). For an address bit to be ‘0’, the corresponding ID pin must be driven High,
V_IH (and there will be a leakage current of I_LI2 through the pin, as specified in Table 24). For
details, see Table 5.
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