E-L6205PD Datasheet, PDF (12/21 Pages) STMicroelectronics – DMOS DUAL FULL BRIDGE DRIVER

L6205
APPLICATION INFORMATION
A typical application using L6205 is shown in Fig. 11. Typical component values for the application are shown
in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power
pins (VS_A and VS_B) and ground near the L6205 to improve the high frequency filtering on the power supply and
reduce high frequency transients generated by the switching. The capacitors connected from the EN_A and EN_B
inputs to ground set the shut down time for the Brgidge A and Bridge B respectively when an over current is
detected (see Overcurrent Protection). The two current sources (SENSE_A and SENSE_B) should be connected
to Power Ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic
pins (except EN_A and EN_B) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin
description). It is recommended to keep Power Ground and Signal Ground separated on PCB.
Table 2. Component Values for Typical Application
C₁
100uF
D₁
C₂
100nF
D₂
C_BOOT
220nF
R_ENA
C_P
10nF
R_ENB
C_ENA
5.6nF
R_P
C_ENB
5.6nF
Figure 11. Typical Application
+
VS
8-52V_DC
C₁
POWER
GROUND
-
SIGNAL
GROUND
VS_{A 17}
C₂
VS_{B 14}
D₁
R_P
VCP
19
C_BOOT
D₂
C_P
VBOOT
12
SENSE_{A 3}
SENSE_{B 8}
LOAD_A
OUT1_{A 4}
OUT2_{A 18}
LOAD_B
OUT1_{B 7}
OUT2_{B 13}
1N4148
1N4148
100kΩ
100kΩ
100Ω
EN_A ^RENA
20
C_ENA
EN_B ^RENB
11
C_ENB
9 ^IN1B
10 ^IN2B
1 ^IN1A
2 ^IN2A
16
GND
15
GND
6
GND
5
GND
D02IN1345
ENABLE_A
ENABLE_B
IN1_B
IN2_B
IN1_A
IN2_A
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