STD9N40M2 Datasheet, PDF (1/16 Pages) STMicroelectronics – Low gate input resistance

STD9N40M2
N-channel 400 V, 0.59 Ω typ., 6 A MDmesh II Plus™ low Q_g
Power MOSFET in a DPAK package
Datasheet - preliminary data
Features
TAB
3
1
DPAK
Figure 1. Internal schematic diagram
, TAB
Order code
STD9N40M2
V_DS @ T_Jmax R_DS(on) max I_D
450 V
0.8 Ω
6A
• Extremely low gate charge
• Lower R_DS(on) x area vs previous generation
• Low gate input resistance
• 100% avalanche tested
• Zener-protected
Applications
• Switching applications
Description
This device is an N-channel Power MOSFET
developed using a new generation of MDmesh™
technology: MDmesh II Plus™ low Q_g. This
revolutionary Power MOSFET associates a
vertical structure to the company's strip layout to
yield one of the world's lowest on-resistance and
gate charge. It is therefore suitable for the most
demanding high efficiency converters.
AM15572v1
Order code
STD9N40M2
Table 1. Device summary
Marking
Package
9N40M2
DPAK
Packaging
Tape and reel
June 2014
DocID025752 Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/16
www.st.com