SST12LP08 Datasheet, PDF (89/98 Pages) Silicon Storage Technology, Inc – 2.4 GHz High-Power, High-Gain Power Amplifier

256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Read Specifications
Figure 34: Continuous Burst Read with Output Delay (ADV# LOW)
CLK
A
ADV#
CE#
OE#
WAIT
DQ
t_AVCH
t_VLCH t_CHAX
t_AVVH
t_AVQV
t_VHVL
t_ELCH
t_ELVH
t_VHAX
t_ELQV
t_CHQV
t_CHQV
t_CHQV
t_GLTV
t_CHTV
t_CHTX
t_GLQV
t_GLQX
t_CHQV
t_CHQX
t_CHQX
t_CHQX
t_CHQX
Notes:
1. WAIT is driven per OE# assertion during synchronous array or nonarray read and can be
configured to assert either during or one data cycle before valid data.
2. At the end of a wordline; the delay incurred when a burst access crosses a 16-word
boundary and the starting address is not 4-word boundary aligned.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. B 8/13 EN
89
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