SST12LP08 Datasheet, PDF (26/98 Pages) Silicon Storage Technology, Inc – 2.4 GHz High-Power, High-Gain Power Amplifier

256Mb and 512Mb (256Mb/256Mb), P30-65nm
Device Command Codes
Table 10: Command Codes and Definitions (Continued)
Mode
Erase
Device Mode
Block erase setup
Block erase confirm
Suspend
Program or erase
suspend
Protection
Suspend resume
Block lock setup
Block lock
Block unlock
Block lock down
OTP register or lock
register program set-
up
Configuration Read configuration
register setup
Read configuration
register
Code
0x20
0xD0
0xB0
0xD0
0x60
0x01
0xD0
0x2F
0xC0
0x60
0x03
Description
First cycle of a two-cycle command; prepares the CUI for a BLOCK
ERASE operation. The device performs the erase algorithm on the
block addressed by the ERASE CONFIRM command. If the next com-
mand is not the ERASE CONFIRM (0xD0) command, the CUI sets status
register bits SR4 and SR5, and places the device in read status register
mode.
If the first command was BLOCK ERASE SETUP (0x20), the CUI latches
the address and data, and the device erases the addressed block. Dur-
ing BLOCK ERASE operations, the device responds only to READ STATUS
REGISTER and ERASE SUSPEND commands. CE# or OE# must be toggled
to update the status register in asynchronous read. CE# or ADV# must
be toggled to update the status register data for synchronous non-ar-
ray reads.
This command issued to any device address initiates a suspend of the
currently-executing program or BLOCK ERASE operation. The status
register indicates successful suspend operation by setting either SR2
(program suspended) or SR6 (erase suspended), along with SR7 (ready).
The device remains in the suspend mode regardless of control signal
states (except for RST# asserted).
This command issued to any device address resumes the suspended
PROGRAM or BLOCK ERASE operation.
First cycle of a two-cycle command; prepares the CUI for block lock con-
figuration changes. If the next command is not BLOCK LOCK (0x01),
BLOCK UNLOCK (0xD0), or BLOCK LOCK DOWN (0x2F), the CUI sets sta-
tus register bits SR5 and SR4, indicating a command sequence error.
If the previous command was BLOCK LOCK SETUP (0x60), the addressed
block is locked.
If the previous command was BLOCK LOCK SETUP (0x60), the addressed
block is unlocked. If the addressed block is in a lock down state, the op-
eration has no effect.
If the previous command was BLOCK LOCK SETUP (0x60), the addressed
block is locked down.
First cycle of a two-cycle command; prepares the device for a OTP REG-
ISTER or LOCK REGISTER PROGRAM operation. The second cycle latches
the register address and data, and starts the programming algorithm
to program data the OTP array.
First cycle of a two-cycle command; prepares the CUI for device read
configuration. If the SET READ CONFIGURATION REGISTER command
(0x03) is not the next command, the CUI sets status register bits SR4
and SR5, indicating a command sequence error.
If the previous command was READ CONFIGURATION REGISTER SETUP
(0x60), the CUI latches the address and writes A[16:1] to the read con-
figuration register for Easy BGA and TSOP, A[15:0] for QUAD+. Follow-
ing a CONFIGURE READ CONFIGURATION REGISTER command, subse-
quent READ operations access array data.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. B 8/13 EN
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