SST12LP08 Datasheet, PDF (82/98 Pages) Silicon Storage Technology, Inc – 2.4 GHz High-Power, High-Gain Power Amplifier

256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Test Conditions and Capacitance
AC Test Conditions and Capacitance
Figure 27: AC Input/Output Reference Timing
V_CCQ
0V
Input V_CCQ/2
Test points
V_CCQ/2 output
Note:
1. AC test inputs are driven at V_CCQ for logic 1 and at 0V for logic 0. Input/output timing
begins/ends at V_CCQ/2. Input rise and fall times (10% to 90%) <5ns. Worst-case speed oc-
curs at V_CC = V_CC (MIN).
Figure 28: Transient Equivalent Load Circuit
Device under
test
Out
C_L
Notes: 1. See the Test Configuration for Worst-Case Speed Conditions table for component values.
2. CL includes jig capacitance.
Table 42: Test Configuration: Worst-Case Speed Condition
Test Configuration
V_CCQ(MIN) standard test
Figure 29: Clock Input AC Waveform
C_L (pF)
30
V_IH
CLK
V_IL
t_CH/CL
t_CLK
t_FCLK/RCLK
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. B 8/13 EN
82
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