W149 Datasheet, PDF (6/15 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

W149
Writing Data Bytes
Each bit in Data Bytes 0–7 control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Table 6 details additional frequency selections that are
available through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0–7 Serial Configuration Map
Affected Pin
Bit(s) Pin No. Pin Name
Data Byte 0
7
--
--
6
--
--
5
--
--
4
--
--
3
--
--
2
--
--
1–0
--
--
Data Byte 1
7
--
6
--
5
--
4
--
3
40
2
--
1
43
0
44
Data Byte 2
7
--
6
7
5
--
4
13
3
12
2
11
1
10
0
8
Data Byte 3
7
--
6
--
5
26
4
25
3
--
2
21, 20,
18, 17
--
--
--
--
SDRAM12
--
CPU1
CPU0
--
PCI_F
--
PCI5
PCI4
PCI3
PCI2
PCI1
--
--
48MHz
24MHz
--
SDRAM8:11
Control Function
Bit Control
0
1
Don’t Care
--
--
SEL_2
See Table 6
SEL_1
See Table 6
SEL_0
See Table 6
Hardware/Software Frequency Select
Hardware Software
Don’t Care
--
--
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Function (See Table 7 for function details)
Normal Operation
(Reserved)
Normal Operation
All Outputs Three-stated
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
--
--
--
--
--
--
--
--
Low
Active
--
--
Low
Active
Low
Active
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
Low
Active
--
--
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
--
--
--
--
Low
Active
Low
Active
--
--
Low
Active
Default
0
0
0
0
0
0
00
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
0
1
Rev 1.0, November 21, 2006
Page 6 of 15