W149 Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

W149
W149
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Single chip system frequency synthesizer for Intel^®
440BX AGPset
• Two copies of CPU output
• Six copies of PCI output
• One 48 MHz output for USB
• One 24 MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Spread Spectrum feature always enabled
• SMBus interface for programming
• Power management control inputs
• Smooth CPU frequency switching from 66.8–124 MHz
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew:............................................. 500 ps
V_DDQ3: ..................................................................... 3.3V±5%
V_DDQ2: ..................................................................... 2.5V±5%
SDRAMIN to SDRAM0:12 Delay:.......................... 3.7 ns typ.
Table 1. Mode Input Table^[1]
Mode
Pin 2
0
PCI_STOP#
1
REF0
Table 2. Pin Selectable Frequency
Input Address _CPU0:1
FS2 FS1 FS0 (MHz)
PCI_F, 1:5
(MHz)
111
100 33.3 (CPU/3)
110
(Reserved)
101
100 33.3 (CPU/3)
100
103 34.3 (CPU/3)
011
66.8 33.4 (CPU/2)
010
83.3 41.7 (CPU/2)
001
66.8 33.4 (CPU/2)
000
124 41.3 (CPU/3)
Spread%
–0.5
±0.5
–0.5
–0.5
–0.5
±0.5
–0.5
Logic Block Diagram
X1
XTAL
X2
OSC
PLL Ref Freq
I/O Pin
Control
PLL 1
÷2/÷3
Stop
Clock
Control
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
VDDQ3
PCI_F/MODE
PCI1
PCI2
PCI3
PCI4
Pin Configuration^[2]
VDDQ3 1
REF0/(PCI_STOP#) 2
GND 3
X1 4
X2 5
VDDQ3 6
PCI_F/MODE 7
PCI1 8
GND 9
PCI2 10
PCI3 11
PCI4 12
PCI5 13
VDDQ3 14
SDRAMIN 15
GND 16
SDRAM11 17
SDRAM10 18
VDDQ3 19
SDRAM9 20
SDRAM8 21
GND 22
{ SMBus SDATA 23
SCLK 24
48 VDDQ2
47 IOAPIC
46 REF1/FS2*
45 GND
44 CPU0
43 CPU1
42 VDDQ2
41 OE
40 SDRAM12
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS0*
25 24MHz/FS1*
SDATA
SCLK
SMBus
Logic
PCI5
PLL2
VDDQ3
48MHz/FS0
÷2
SDRAMIN
24MHz/FS1
VDDQ3
SDRAM0:12
13
Notes:
1. Mode input latched at power-up.
2. Internal pull up resistors(*) should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
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