W149 Datasheet, PDF (2/15 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

W149
Pin Definitions
Pin Name
Pin No. Pin Type
Pin Description
CPU0:1
44, 43
O CPU Clock Outputs: See Tables 2 and 6 for detailed frequency information. Output
voltage swing is controlled by voltage applied to VDDQ2.
PCI1:5
8, 10, 11, 12,
13
O PCI Clock Outputs 1 through 5: These five PCI clock outputs are controlled by
the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
PCI_F/MODE
7
I/O Fixed PCI Clock Output: Frequency is set by the FS0:1 inputs or through serial
input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP#
input. Upon power-up the mode input will be latched, which will determine the
function of pin 2, REF0/(PCI_STOP#). See Table 1.
OE
41
I
Output Enable Input: When brought LOW, all outputs are placed in a
high-impedance state. When brought HIGH, all clock outputs activate.
IOAPIC
47
O IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is controlled by VDDQ2.
48MHz/FS0
26
I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this
output can be used as the reference for the Universal Serial Bus. Upon power-up,
FS0 input will be latched, which will set clock frequencies as described in Table 2.
This output does not have the Spread Spectrum feature.
24MHz/FS1
25
I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this
output can be used as the clock input for a Super I/O chip. Upon power-up FS1
input will be latched, which will set clock frequencies as described in Table 2. This
output does not have the Spread Spectrum feature.
REF1/FS2
46
I/O I/O Dual-Function REF1 and FS2 pin: Upon power-up, FS2 input will be latched
which will set clock frequencies as described in Table 2. When an output, this pin
provides a fixed clock signal equal in frequency to the reference signal provided at
the X1/X2 pins.
REF0/
2
(PCI_STOP#)
I/O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function is determined by the
MODE input. When set as an input, the PCI_STOP# input enables the PCI 1:5
outputs when HIGH and causes them to remain at logic 0 when LOW. The
PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on
the next PCI_F clock cycle. When an output, this pin provides a fixed clock signal
equal in frequency to the reference signal provided at the X1/X2 pins.
SDRAMIN
15
I
Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs
(SDRAM0:12).
SDRAM0:12 38, 37, 35,
Buffered Outputs: These thirteen dedicated outputs provide copies of the signal
34, 32, 31,
O provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deacti-
29, 28, 21,
vated when CLK_STOP# input is set LOW.
20, 18, 17, 40
SCLK
24
I
Clock pin for SMBus circuitry.
SDATA
23
I/O Data pin for SMBus circuitry.
X1
4
I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2
5
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
VDDQ3
1, 6, 14, 19,
27, 30, 36
P
Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs,
PCI outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to
3.3V supply.
VDDQ2
42, 48
P
Power Connection: Power supply for IOAPIC and CPU0:1 output buffers. Connect
to 2.5V, or 3.3V.
GND
3, 9, 16, 22,
33, 39, 45
G Ground Connections: Connect all ground pins to the common system ground
plane.
Rev 1.0, November 21, 2006
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