W149 Datasheet, PDF (12/15 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

W149
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
CPU = 66.6 MHz
Parameter
Description
Test Condition/Comments Min. Typ. Max.
t_P
Period
t_H
High Time
Measured on rising edge at 1.5V 30
Duration of clock cycle above 2.4V, 5.6
at min. sdge rate (1.5 V/ns)
t_L
Low Time
Duration of clock cycle below 0.4V, 5.3
at min. sdge rate (1.5 V/ns)
t_R
Output Rise Edge Measured from 0.4V to 2.4V
1.5
4
Rate
t_F
Output Fall Edge
Measured from 2.4V to 0.4V
1.5
4
Rate
t_PLH
Prop Delay LH
Input edge rate faster than 1 V/ns 1
5
t_PHL
Prop Delay HL
Input edge rate faster than 1 V/ns 1
5
t_D
Duty Cycle
Measured on rising and falling
45
55
edge at 1.5V, at min. sdge rate
(1.5 V/ns)
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V.
250
Maximum difference of cycle time
between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V
250
t_O
CPU to PCI Clock Covers all CPU/PCI outputs.
1.5
4
Skew
Measured on rising edge at 1.5V.
CPU leads PCI output.
f_ST
Frequency
Assumes full supply voltage
3
Stabilization from
reached within 1 ms from
Power-up (cold start) power-up. Short cycles exist prior
to frequency stabilization.
Z_o
AC Output
Average value during switching
30
Impedance
transition. Used for determining
series termination value.
CPU = 100 MHz
Min. Typ. Max. Unit
30
ns
3.3
ns
3.1
ns
1.5
4 V/ns
1.5
4 V/ns
1
5 ns
1
5 ns
45
55 %
250 ps
250 ps
1.5
4 ns
3 ms
30
:
Rev 1.0, November 21, 2006
Page 12 of 15