W149 Datasheet, PDF (3/15 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

W149
Overview
The W149 was developed as a single chip device to meet the
clocking needs of the Intel 440BX AGPset. In addition to the
typical outputs provided by standard 100-MHz 440BX AGPset
FTGs, the W149 adds a thirteen output buffer, supporting
SDRAM DIMM modules in conjunction with the chipset.
Cypress proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. This
feature reduces the peak EMI measurements of not only the
output signals and their harmonics, but also of any other clock
signals that are properly synchronized to them.
Functional Description
I/O Pin Operation
Pins 7, 25, 26, 46 are dual-purpose l/O pins. Upon power-up
these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-k: “strapping” resistor is connected between
the l/O pin and ground or V_DD. Connection to ground sets a
latch to “0”, connection to V_DD sets a latch to “1”. Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W149 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the four I/O pins (7,
25, 26, 46) are three-stated, allowing the output strapping
resistor on the l/O pins to pull each pin and its associated
capacitive clock load to either a logic HIGH or LOW state. At
the end of the 2-ms period, the established logic “0” or “1”
condition of the l/O pin is latched. Next the output buffer is
enabled, converting the l/O pins into operating clock outputs.
The 2-ms timer starts when V_DD reaches 2.0V. The input bits
can only be reset by turning V_DD off and then back on again.
It should be noted that the strapping resistors have no signif-
icant effect on clock output signal integrity. The drive
impedance of clock output is <40: (nominal), which is
minimally affected by the 10-k: strap to ground or V_DD. As
with the series termination resistor, the output strapping
resistor should be placed as close to the l/O pin as possible in
order to keep the interconnecting trace short. The trace from
the resistor to ground or V_DD should be kept less than two
inches in length to prevent system noise coupling during input
logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that V_DD has stabilized. If V_DD has not yet reached
full value, output frequency initially may be below target but will
increase to target once V_DD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
W149
Power-on
Reset
Timer
V_DD
Output
Buffer
Output Three-state Hold
Output
Low
QD
Data
Latch
10 k:
(Load Option 1)
10 k:
(Load Option 0)
Output Strapping Resistor
Series Termination Resistor
Clock Load
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
W149
Power-on
Reset
Timer
Output
Buffer
Output Three-state Hold
Output
Low
QD
Data
Latch
10 k:
V_DD
Output Strapping Resistor
Series Termination Resistor
R
Clock Load
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Option
Rev 1.0, November 21, 2006
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