S25FL128S Datasheet, PDF (98/153 Pages) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Data Sheet
1. During the Dual I/O Enhanced High Performance Command Sequence, if the Mode bits are any
value other than Axh, then the next time CS# is raised high the device will be released from Dual
I/O Read Enhanced High Performance Read mode.
During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0 and IO1)
are not set for a valid instruction sequence, then the device will be released from Dual I/O Enhanced High
Performance Read mode. Note that the four mode bit cycles are part of the device’s internal circuitry latency
time to access the initial address after the last address cycle that is clocked into IO0 (SI) and IO1 (SO).
It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out
clock. At higher clock speeds the time available to turn off the host outputs before the memory device begins
to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing I/O signal contention,
for the host system to turn off the I/O signal outputs (make them high impedance) during the last two “don’t
care” mode cycles or during any dummy cycles.
Following the latency period the memory content, at the address given, is shifted out two bits at a time
through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK
signal.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
Figure 10.33 Dual I/O Read Command Sequence (3-byte Address, BBh [ExtAdd=0], HPLC=00b)
CS#
SCLK
IO0
IO1
Phase
7 6 5 4 3 2 1 0 22 20 18 0
23 21 19 1
Instruction
Address
4 Dummy
6 42 06 42 0
7 53 17 53 1
Data 1
Data 2
Figure 10.34 Dual I/O Read Command Sequence (4-byte Address, BBh [ExtAdd=1], HPLC=10b)
CS#
SCLK
IO0
IO1
Phase
7 6 5 4 3 2 1 0 30 28 26 0
31 29 27 1
Instruction
Address
6 Dummy
6 42 06 42 0
7 53 17 53 1
Data 1
Data 2
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S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012