S25FL128S Datasheet, PDF (116/153 Pages) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Data Sheet
Figure 10.61 Parameter Sector Erase Command Sequence (3-byte Address, 20h)
CS#
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
Instruction
24 Bit Address
23 22 21
MSB
3210
Figure 10.62 Parameter Sector Erase Command Sequence
(ExtAdd = 1, 20h or 4-byte Address, 21h)
CS#
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39
Instruction
32 Bit Address
31 30 29
MSB
3210
10.6.2
Sector Erase (SE D8h or 4SE DCh)
The Sector Erase (SE) command sets all bits in the addressed sector to 1 (all bytes are FFh). Before the
Sector Erase (SE) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable
any write operations.
The instruction
 D8h [ExtAdd=0] is followed by a 3-byte address (A23-A0), or
 D8h [ExtAdd=1] is followed by a 4-byte address (A31-A0), or
 DCh is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of address has been
latched in on SI. This will initiate the erase cycle, which involves the pre-programming and erase of the
chosen sector. If CS# is not driven high after the last bit of address, the sector erase operation will not be
executed.
As soon as CS# is driven into the logic high state, the internal erase cycle will be initiated. With the internal
erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the
operation has been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a0 when
the erase cycle has been completed.
A Sector Erase (SE) command applied to a sector that has been Write Protected through the Block Protection
bits or ASP, will not be executed and will set the E_ERR status.
116
S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012