S25FL128S Datasheet, PDF (129/153 Pages) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

CS#
Data Sheet
Figure 10.82 Software Reset Command Sequence
SCK
SI
01234567
Instruction
10.9.2
Mode Bit Reset (MBR FFh)
The Mode Bit Reset (MBR) command can be used to return the device from continuous high performance
read mode back to normal standby awaiting any new command. Because some device packages lack a
hardware RESET# input and a device that is in a continuous high performance read mode may not recognize
any normal SPI command, a system hardware reset or software reset command may not be recognized by
the device. It is recommended to use the MBR command after a system reset when the RESET# signal is not
available or, before sending a software reset, to ensure the device is released from continuous high
performance read mode.
The MBR command sends Ones on SI or IO0 for 8 SCK cycles. IO1 to IO3 are “don’t care” during these
cycles.
Figure 10.83 Mode Bit Reset Command Sequence
CSS#
SCK
SI
SO
0 12 3 4 5 6 7
Instruction (FFh)
High Impedance
July 12, 2012 S25FL128S_256S_00_05
S25FL128S and S25FL256S
129