S25FL128S Datasheet, PDF (128/153 Pages) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Data Sheet
10.8.12
Password Unlock (PASSU E9h)
The PASSU command is entered by driving CS# to the logic low state, followed by the instruction and the
password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is
sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64^th) bit of data has been latched. If not, the
PASSU command is not executed. As soon as CS# is driven to the logic high state, the self-timed PASSU
operation is initiated. While the PASSU operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PASSU
cycle, and is a 0 when it is completed.
If the PASSU command supplied password does not match the hidden password in the Password Register,
an error is reported by setting the P_ERR bit to 1. The WIP bit of the status register also remains set to 1. It is
necessary to use the CLSR command to clear the status register, the RESET command to software reset the
device, or drive the RESET# input low to initiate a hardware reset, in order to return the P_ERR and WIP bits
to 0. This returns the device to standby state, ready for new commands such as a retry of the PASSU
command.
If the password does match, the PPB Lock bit is set to 1. The maximum clock frequency for the PASSU
command is 133 MHz.
Figure 10.81 Password Unlock Command Sequence
CS#
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10
68 69 70 71
Instruction
Password
7654321 0 765
MSB
High Impedance
MSB
59 58 57 56
10.9 Reset Commands
10.9.1
Software Reset Command (RESET F0h)
The Software Reset command (RESET) restores the device to its initial power up state, except for the volatile
FREEZE bit in the Configuration register CR1[1] and the volatile PPB Lock bit in the PPB Lock Register. The
Freeze bit and the PPB Lock bit will remain set at their last value prior to the software reset. To clear the
FREEZE bit and set the PPB Lock bit to its protection mode selected power on state, a full power-on-reset
sequence or hardware reset must be done. Note that the non-volatile bits in the configuration register,
TBPROT, TBPARM, and BPNV, retain their previous state after a Software Reset. The Block Protection bits
BP2, BP1, and BP0, in the status register will only be reset if they are configured as volatile via the BPNV bit
in the Configuration Register (CR1[3]) and FREEZE is cleared to zero . The software reset cannot be used to
circumvent the FREEZE or PPB Lock bit protection mechanisms for the other security configuration bits. The
reset command is executed when CS# is brought to high state and requires t_RPH time to execute.
128
S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012