S25FL128S Datasheet, PDF (100/153 Pages) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Data Sheet
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled
through the setting of the Mode bits (after the address sequence, as shown in Figure 10.37 on page 100 or
Figure 10.39 on page 101). This added feature removes the need for the instruction sequence and greatly
improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next
Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits
3-0) of the Mode bits are “don’t care” (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O
High Performance Read Mode and the next address can be entered (after CS# is raised high and then
asserted low) without requiring the EBh or ECh instruction, as shown in Figure 10.38 on page 101 or
Figure 10.40 on page 102; thus, eliminating eight cycles for the command sequence. The following
sequences will release the device from Quad I/O High Performance Read mode; after which, the device can
accept standard SPI commands:
1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh,
then the next time CS# is raised high the device will be released from Quad I/O High Performance
Read mode.
During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0-IO3) are
not set for a valid instruction sequence, then the device will be released from Quad I/O High Performance
Read mode. Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the
device’s internal circuitry latency time to access the initial address after the last address cycle that is clocked
into IO0-IO3.
It is important that the IO0-IO3 signals be set to high-impedance at or before the falling edge of the first data
out clock. At higher clock speeds the time available to turn off the host outputs before the memory device
begins to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing IO0-IO3 signal
contention, for the host system to turn off the IO0-IO3 signal outputs (make them high impedance) during the
last “don’t care” mode cycle or during any dummy cycles.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
Figure 10.37 Quad I/O Read Command Sequence (3-byte Address, EBh [ExtAdd=0], LC=00b)
CS#
012345678
12 13 14 15 16 17 18 19 20 21 22 23
SCLK
8 cycles
Instruction
6 cycles
24 Bit Address
2 cycles
Mode
IO0 7 6 5 4 3 2 1 0 20
40 40
IO1
21
51 51
IO2
22
62 62
3
IO3
23
73 7
4 cycles
Dummy
2 cycles
Data 1
40
Data 2
40
5151
6261
7371
100
S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012