S25FL128SDPMFIG11 Datasheet, PDF (92/153 Pages) SPANSION – MirrorBit Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Data Sheet
10.4
Read Memory Array Commands
Read commands for the main flash array provide many options for prior generation SPI compatibility or
enhanced performance SPI:
 Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate
commands (SDR).
 Some SDR commands transfer address one bit per rising edge of SCK and return data 1, 2, or 4 bits of
data per rising edge of SCK. These are called Read or Fast Read for 1-bit data; Dual Output Read for 2-bit
data, and Quad Output for 4-bit data.
 Some SDR commands transfer both address and data 2 or 4 bits per rising edge of SCK. These are called
Dual I/O for 2 bit and Quad I/O for 4 bit.
 Some commands transfer address and data on both the rising edge and falling edge of SCK. These are
called Double Data Rate (DDR) commands.
 There are DDR commands for 1, 2, or 4 bits of address or data per SCK edge. These are called Fast DDR
for 1-bit, Dual I/O DDR for 2-bit, and Quad I/O DDR for 4-bit per edge transfer.
All of these commands begin with an instruction code that is transferred one bit per SCK rising edge. The
instruction is followed by either a 3- or 4-byte address transferred at SDR or DDR. Commands transferring
address or data 2 or 4 bits per clock edge are called Multiple I/O (MIO) commands. For FL-S devices at
256 Mbits or higher density, the traditional SPI 3-byte addresses are unable to directly address all locations in
the memory array. These device have a bank address register that is used with 3-byte address commands to
supply the high order address bits beyond the address from the host system. The default bank address is
zero. Commands are provided to load and read the bank address register. These devices may also be
configured to take a 4-byte address from the host system with the traditional 3-byte address commands. The
4-byte address mode for traditional commands is activated by setting the External Address (EXTADD) bit in
the bank address register to 1. In the FL128S, higher order address bits above A23 in the 4-byte address
commands, commands using Extended Address mode, and the Bank Address Register are not relevant and
are ignored because the flash array is only 128 Mbits in size.
The Quad I/O commands provide a performance improvement option controlled by mode bits that are sent
following the address bits. The mode bits indicate whether the command following the end of the current read
will be another read of the same type, without an instruction at the beginning of the read. These mode bits
give the option to eliminate the instruction cycles when doing a series of Quad I/O read accesses.
A device ordering option provides an enhanced high performance option by adding a similar mode bit scheme
to the DDR Fast Read, Dual I/O, and Dual I/O DDR commands, in addition to the Quad I/O command.
Some commands require delay cycles following the address or mode bits to allow time to access the memory
array. The delay cycles are traditionally called dummy cycles. The dummy cycles are ignored by the memory
thus any data provided by the host during these cycles is “don’t care” and the host may also leave the SI
signal at high impedance during the dummy cycles. When MIO commands are used the host must stop
driving the IO signals (outputs are high impedance) before the end of last dummy cycle. When DDR
commands are used the host must not drive the I/O signals during any dummy cycle. The number of dummy
cycles varies with the SCK frequency or performance option selected via the Configuration Register 1 (CR1)
Latency Code (LC). Dummy cycles are measured from SCK falling edge to next SCK falling edge. SPI
outputs are traditionally driven to a new value on the falling edge of each SCK. Zero dummy cycles means the
returning data is driven by the memory on the same falling edge of SCK that the host stops driving address or
mode bits.
The DDR commands may optionally have an 8-edge Data Learning Pattern (DLP) driven by the memory, on
all data outputs, in the dummy cycles immediately before the start of data. The DLP can help the host
memory controller determine the phase shift from SCK to data edges so that the memory controller can
capture data at the center of the data eye.
When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides 1 or more
dummy cycles should be selected to allow additional time for the host to stop driving before the memory starts
driving data, to minimize I/O driver conflict. When using DDR I/O commands with the DLP enabled, an LC
that provides 5 or more dummy cycles should be selected to allow 1 cycle of additional time for the host to
stop driving before the memory starts driving the 4 cycle DLP.
Each read command ends when CS# is returned High at any point during data return. CS# must not be
returned High during the mode or dummy cycles before data returns as this may cause mode bits to be
92
S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012