S25FL128SDPMFIG11 Datasheet, PDF (61/153 Pages) SPANSION – MirrorBit Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Data Sheet
Freq.
(MHz)
LC
≤ 50 11
≤ 80 00
≤ 90 01
≤104 10
≤133 10
Table 8.12 Latency Codes for SDR Enhanced High Performance
Read
(03h, 13h)
Mode Dummy
0
0
-
-
-
-
-
-
-
-
Fast Read
(0Bh, 0Ch)
Mode Dummy
0
0
0
8
0
8
0
8
0
8
Read Dual Out
(3Bh, 3Ch)
Mode Dummy
0
0
0
8
0
8
0
8
-
-
Read Quad Out
(6Bh, 6Ch)
Mode Dummy
0
0
0
8
0
8
0
8
-
-
Dual I/O Read
(BBh, BCh)
Mode Dummy
4
0
4
0
4
1
4
2
-
-
Quad I/O Read
(EBh, ECh)
Mode Dummy
2
1
2
4
2
4
2
5
-
-
Freq.
(MHz)
LC
≤ 50
11
≤ 66
00
≤ 66
01
≤ 66
10
Table 8.13 Latency Codes for DDR Enhanced High Performance
DDR Fast Read
(0Dh, 0Eh)
Mode
Dummy
4
1
4
2
4
4
4
5
DDR Dual I/O Read
(BDh, BEh)
Mode
Dummy
2
2
2
4
2
5
2
6
Read DDR Quad I/O
(EDh, EEh)
Mode
Dummy
1
3
1
6
1
7
1
8
Top or Bottom Protection (TBPROT) CR1[5]: This bit defines the operation of the Block Protection bits
BP2, BP1, and BP0 in the Status Register. As described in the status register section, the BP2-0 bits allow
the user to optionally protect a portion of the array, ranging from 1/64, 1/4, 1/2, etc., up to the entire array.
When TBPROT is set to a 0 the Block Protection is defined to start from the top (maximum address) of the
array. When TBPROT is set to a 1 the Block Protection is defined to start from the bottom (zero address) of
the array. The TBPROT bit is OTP and set to a 0 when shipped from Spansion. If TBPROT is programmed to
1, an attempt to change it back to 0 will fail and set the Program Error bit (P_ERR in SR1[6]).
The desired state of TBPROT must be selected during the initial configuration of the device during system
manufacture; before the first program or erase operation on the main flash array. TBPROT must not be
programmed after programming or erasing is done in the main flash array.
CR1[4]: Reserved for Future Use
Block Protection Non-Volatile (BPNV) CR1[3]: The BPNV bit defines whether or not the BP2-0 bits in the
Status Register are volatile or non-volatile. The BPNV bit is OTP and cleared to a0 with the BP bits cleared to
000 when shipped from Spansion. When BPNV is set to a 0 the BP2-0 bits in the Status Register are non-
volatile. When BPNV is set to a 1 the BP2-0 bits in the Status Register are volatile and will be reset to binary
111 after POR, hardware reset, or command reset. If BPNV is programmed to 1, an attempt to change it back
to 0 will fail and set the Program Error bit (P_ERR in SR1[6]).
TBPARM CR1[2]: TBPARM defines the logical location of the parameter block. The parameter block consists
of thirty-two 4-kB small sectors (SMS), which replace two 64-kB sectors. When TBPARM is set to a 1 the
parameter block is in the top of the memory array address space. When TBPARM is set to a 0 the parameter
block is at the Bottom of the array. TBPARM is OTP and set to a 0 when it ships from Spansion. If TBPARM
is programmed to 1, an attempt to change it back to 0 will fail and set the Program Error bit (P_ERR in
SR1[6]).
The desired state of TBPARM must be selected during the initial configuration of the device during system
manufacture; before the first program or erase operation on the main flash array. TBPARM must not be
programmed after programming or erasing is done in the main flash array.
TBPROT can be set or cleared independent of the TBPARM bit. Therefore, the user can elect to store
parameter information from the bottom of the array and protect boot code starting at the top of the array, and
vice versa. Or the user can select to store and protect the parameter information starting from the top or
bottom together.
When the memory array is logically configured as uniform 256-kB sectors, the TBPARM bit is Reserved for
Future Use (RFU) and has no effect because all sectors are uniform size.
July 12, 2012 S25FL128S_256S_00_05
S25FL128S and S25FL256S
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