S25FL128SDPMFIG11 Datasheet, PDF (56/153 Pages) SPANSION – MirrorBit Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Data Sheet
8.3
8.4
ID-CFI Address Space
The RDID command (9Fh) reads information from a separate flash memory address space for device
identification (ID) and Common Flash Interface (CFI) information. See Device ID and Common Flash
Interface (ID-CFI) Address Map on page 133 for the tables defining the contents of the ID-CFI address space.
The ID-CFI address space is programmed by Spansion and read-only for the host system.
OTP Address Space
Each S25FL128S and S25FL256S memory device has a 1024-byte One Time Program (OTP) address space
that is separate from the main flash array. The OTP area is divided into 32, individually lockable, 32-byte
aligned and length regions.
In the 32-byte region starting at address zero:
 The 16 lowest address bytes are programmed by Spansion with a 128-bit random number. Only Spansion
is able to program these bytes.
 The next 4 higher address bytes (OTP Lock Bytes) are used to provide one bit per OTP region to
permanently protect each region from programming. The bytes are erased when shipped from Spansion.
After an OTP region is programmed, it can be locked to prevent further programming, by programming the
related protection bit in the OTP Lock Bytes.
 The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in
these RFU bytes may be programmed by the host system but it must be understood that a future device
may use those bits for protection of a larger OTP space. The bytes are erased when shipped from
Spansion.
The remaining regions are erased when shipped from Spansion, and are available for programming of
additional permanent data.
Refer to Figure 8.1, OTP Address Space on page 57 for a pictorial representation of the OTP memory space.
The OTP memory space is intended for increased system security. OTP values, such as the random number
programmed by Spansion, can be used to “mate” a flash component with the system CPU/ASIC to prevent
device substitution.
The configuration register FREEZE (CR1[0]) bit protects the entire OTP memory space from programming
when set to 1. This allows trusted boot code to control programming of OTP regions then set the FREEZE bit
to prevent further OTP memory space programming during the remainder of normal power-on system
operation.
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S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012