S71WS-NX0 Datasheet, PDF (88/188 Pages) SPANSION – Stacked Multi-Chip Product (MCP)

Advance Information
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
CLK
Address (hex)
C124 C125 C126 C127 C127
7C
7D
7E
7F
7F
AVD# (stays high)
RDY(1)
RDY(2)
t_RACC
t_RACC
latency
latency
t_RACC
t_RACC
Data
D124 D125 D126
D127
Read Status
OE#, _{(stays low)}
CE#
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device crossing a bank in the process of performing an erase or program.
5. RDY does not go low and no additional wait states are required for WS ≤ 5.
Figure 14.22 Latency with Boundary Crossing into Program/Erase Bank
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S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005