S71WS-NX0 Datasheet, PDF (136/188 Pages) SPANSION – Stacked Multi-Chip Product (MCP)

Advance Information
32.3.2.1 Write Timings
Latency = 5, Burst Length = 4, WP = Low enable (OE# = V_IH, MRS# = V_IH).
CS# Toggling Consecutive Burst Write
CL K
ADV#
0
1
2
3
4
5
6
7
8
9 10 11 12 13
T
tADVH
tADVS
tAS(B)
tAH(B)
tBEADV
Address
Valid
Don’t Care
Valid
tCSS(B)
tBC
tCSHP
CS#
LB#, UB#
WE#
tWES
tWEH
tBS
tBMS
tBH
tBMH
tWHP
Latency 5
tDS
tDHC
tDHC
Latency 5
Data in
WAIT#
tWL
High-Z
D0 D1 D2 D3
tWH
tWZ
tWL
D0
tWH
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t_BEADV should be met.
2. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
3. /WAIT Low (t_WL or t_AWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (t_WH): Data available (driven by Latency-1 clock)
/WAIT High-Z (t_WZ): Data don’t care (driven by CS# high going edge)
4. D2 is masked by UB# and LB#.
5. Burst Cycle Time (t_BC) should not be over 2.5µs.
Figure 32.6 Timing Waveform of Burst Write Cycle (1)
Symbol
t_CSHP
t_BS
t_BH
t_BMS
t_BMH
t_WES
t_WEH
Table 32.5 Burst Write AC Characteristics
Speed
Min
Max
5
—
5
—
5
—
7
—
7
—
5
—
5
—
Units
ns
Symbol
t_WHP
t_DS
t_DHC
t_WL
t_WH
t_WZ
Speed
Min
Max
5
—
5
—
3
—
—
10
—
12
—
7
Units
ns
134
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005