S71WS-NX0 Datasheet, PDF (181/188 Pages) SPANSION – Stacked Multi-Chip Product (MCP)

Advance Information
48.3.5
Synchronous Burst Read Suspend Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= V_IH, MRS# = V_IH).
0
1
2
3
4
5
6
7
8
9
CL K
ADV#
T
tADVH
tADVS
10 11
tAS(B)
tAH(B)
Address
Valid
Don’t Care
tCSS(B)
tBC
CS#
LB#, UB#
OE#
Data out
WAIT#
tBEL
tBLZ
tOEL
tOLZ
Latency 5
tWL
High-Z
tCD
Undefined DQ0
tWH
tOHZ
tOLZ
DQ1 High-Z DQ1
tOH
tHZ
DQ2 DQ3
tWZ
Notes:
1. If the clock input is halted during burst read operation, the data output will be suspended. During the burst read
suspend period, OE# high drives data output to high-Z. If the clock input is resumed, the suspended data will be
output first.
2. /WAIT Low (t_WL or t_AWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (t_WH): Data available (driven by Latency-1 clock)
/WAIT High-Z (t_WZ): Data don’t care (driven by CS# high going edge)
3. During the suspend period, OE# high drives DQ to High-Z and OE# low drives DQ to Low-Z. If OE# stays low during
suspend period, the previous data will be sustained.
4. Burst Cycle Time (t_BC) should not be over 2.5µs.
Figure 48.10 Timing Waveform of Burst Read Suspend Cycle (1)
Symbol
t_BEL
t_OEL
t_BLZ
t_OLZ
t_CD
t_OH
Table 48.9 Burst Read Suspend AC Characteristics
Speed
Min
Max
1
—
1
—
5
—
5
—
—
10
3
—
Units
clock
ns
Symbol
t_HZ
t_OHZ
t_WL
t_WH
t_WZ
Speed
Min
Max
—
10
—
7
—
10
—
12
—
7
Units
ns
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
179