S71WS-NX0 Datasheet, PDF (124/188 Pages) SPANSION – Stacked Multi-Chip Product (MCP)

Advance Information
31.3.2.1 Write Cycle 2
MRS# = V_IH, OE# = V_IH, WAIT# = High-Z, UB# & LB# Controlled
Address
CS#
UB#, LB#
WE#
Data in
tWC
tWR
tCW
tAW
tBW
tAS
tWP
tDW
tDH
Data Valid
Data out
High-Z
High-Z
Notes:
1. A write occurs during the overlap (t_WP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t_WP is measured from the
beginning of write to the end of write.
2. t_CW is measured from the CS# going low to the end of write.
3. t_AS is measured from the address valid to the beginning of write.
4. t_WR is measured from the end of write to the address change. t_WR is applied in case a write ends with CS# or WE#
going high.
5. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 31.5 Timing Waveform of Write Cycle(2)
Table 31.4 Asynchronous Write AC Characteristics (UB# & LB# Controlled)
Speed
Symbol
Min
Max
Units
t_WC
70
—
t_CW
60
—
t_AW
60
—
ns
t_BW
60
—
t_WP
55 (note 1)
—
Note: t_WP(min) = 70ns for continuous write operation over 50 times.
Symbol
t_AS
t_WR
t_DW
t_DH
Speed
Min Max
0
—
0
—
30
—
0
—
Units
ns
122
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005