S71WS-NX0 Datasheet, PDF (182/188 Pages) SPANSION – Stacked Multi-Chip Product (MCP)

Advance Information
49 Transition Timing Waveform Between Read And Write
Latency = 5, Burst Length = 4, WP = Low enable (MRS# = V_IH).
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
T
CL K
ADV#
tADVS
tADVH
tAS(B)
tAH(B)
tBEADV
tAS(A)
tADV
tAH(A)
Address
CS#
WE#
OE#
Valid
Don’t Care
tCSS(B)
tBC
tOEL
Valid
tCSS(A)
tAW
tCW
tWLRL
tWP
tAS
LB#, UB#
Data in
Data out
WAIT#
tBEL
Latency 5
High-Z
tWL
tWH
High-Z
tCD
tOH
tHZ
DQ0 DQ1 DQ2 DQ3
tWZ
tBW
tDW tDH
Data Valid
High-Z
High-Z
Read Latency 5
Notes:
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t_BEADV should be met.
2. /WAIT Low (t_WL or t_AWL): Data not available (driven by CS# low going edge or ADV# low going edge)
/WAIT High (t_WH): Data available (driven by Latency-1 clock)
/WAIT High-Z (t_WZ): Data don’t care (driven by CS# high going edge)
3. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
4. Burst Cycle Time (t_BC) should not be over 2.5µs.
Figure 49.1 Synchronous Burst Read to Asynchronous Write (Address Latch Type)
Table 49.1 Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics
Symbol
t_BEADV
Speed
Min
Max
7
—
Units
ns
Symbol
t_WLRL
Speed
Min
Max
1
—
Units
clock
180
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005