S75WS-N Datasheet, PDF (8/15 Pages) SPANSION – Stacked Multi-Chip Product (MCP)

Preliminary
4 MCP Block Diagram
A0-A22
A23
RDY
CL K
AVD#
F1-CE#
OE#
F-RST#
F-ACC
F1-WP#
F-WE#
A0-A22
A23
RDY
CLK
AVD#
CE#
OE#
RESET#
ACC
WP#
WE#
DQ0-DQ15
WS256N
Flash
Memory
VSS
VCC
VCCQ
DQ0-DQ15
VSS
F-VCC
F-VCCQ
R-CE#
R-LB#
R-UB#
R-MRS#
A0-A22
WAIT#
CLK
AVD#
CE#
OE#
LB#
UB#
WE#
MRS#
DQ0-DQ15
128Mb
Memory
VSS
VCC
VCCQ
R-VCC
R-VCCQ
F2-CE#
FD-WP#
A0-A22
A23
RDY
CLK
AVD#
CE#
OE#
RESET#
ACC
WP#
WE#
DQ0-DQ15
WS256N
Flash
Memory
VSS
VCC
VCCQ
F3-CE#
v
A0-A22
A23
RDY
CLK
AVD#
CE#
OE#
RESET#
ACC
WP#
WE#
DQ0-DQ15
WS256N
Flash
Memory
VSS
VCC
VCCQ
Notes:
1. MRS is only present in RAM Type 4.
2. CE#f1, CE#f2, and CE#f3 are the chip enable pins for the first, second and third Flash devices, respectively.
Figure 4.1 MCP Block Diagram 1
6
S75WS-N Based MCPs
S75WS-N_02_A2 October 6, 2005