S29WS-P Datasheet, PDF (47/89 Pages) SPANSION – 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory

Data Sheet (Advance Information)
7.8
7.9
Table 7.36 Write Operation Status
Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
DQ1
(Note 4)
Standard ^{Embedded Program Algorithm}
Mode _{Embedded Erase Algorithm}
DQ7#
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
N/A
Program
Suspend
Mode
(Note 3)
Reading within Program Suspended Sector
Reading within Non-Program Suspended
Sector
INVALID
(Not
Allowed)
Data
INVALID
(Not
Allowed)
Data
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
Data
Data
Data
INVALID
(Not
Allowed)
Data
Erase
Suspend
Mode
Erase-Suspend-
Read
Erase
Suspended Sector
Non-Erase Suspended
Sector
1
Data
No toggle
Data
0
Data
N/A
Data
Toggle
Data
N/A
Data
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
N/A
Write to
Buffer
(Note 5)
BUSY State
Exceeded Timing Limits
ABORT State
DQ7#
Toggle
0
N/A
N/A
0
DQ7#
Toggle
1
N/A
N/A
0
DQ7#
Toggle
0
N/A
N/A
1
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the
section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer
Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
Simultaneous Read/Program or Erase
The simultaneous read/program or erase feature allows the host system to read data from one bank of
memory while programming or erasing another bank of memory. An erase operation may also be suspended
to read from or program another location within the same bank (except the sector being erased). Figure 11.25
on page 76 shows how read and write cycles may be initiated for simultaneous operation with zero latency.
Refer to DC Characteristics on page 61 for read-while-program and read-while-erase current specification.
Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are allowed, and
CLK is ignored. When in the Synchronous read mode configuration, the device is able to perform both
Asynchronous and Synchronous write operations. CLK and AVD# induced address latches are supported in
the Synchronous programming mode. During a synchronous write operation, to write a command or
command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to V_IL, and OE# to V_IH when providing an address to the device, and drive
WE# and CE# to V_IL, and OE# to V_IH when writing commands or data. During an asynchronous write
operation, the system must drive CE# and WE# to V_IL and OE# to V_IH when providing an address, command,
and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising
edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device.
Table 6.2 on page 14 and Table 6.3 on page 15 indicate the address space that each sector occupies. The
device address space is divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while
Banks 0 and 15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A bank address is the set
of address bits required to uniquely select a bank. Similarly, a sector address is the address bits required to
uniquely select a sector. I_CC2 in DC Characteristics on page 61 represents the active current specification for
the write mode. AC Characteristics-Synchronous and AC Characteristics-Asynchronous contain timing
specification tables and timing diagrams for write operations.
November 8, 2006 S29WS-P_00_A7
S29WS-P
45