S29WS-P Datasheet, PDF(19/89 Page) SPANSION – 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory

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S29WS-P Datasheet, PDF (19/89 Pages) SPANSION – 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory

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Data Sheet (Advance Information)

7.3

Page Mode Read

The device is capable of fast page mode read. This mode provides random read access speed for locations

within a page. Address bits AmaxâA3 select an 8 word page, and address bits A2âA0 select a specific word

within that page. This is an asynchronous operation with the microprocessor supplying the specific word

location. It does not matter if AVD# stays low or toggles once. However, the address input must be always

valid and stable if AVD# is low during the page read.

The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the

locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is

deasserted (=VIH), the reassertion of CE# for subsequent access has access time of tACC or tCE. Here again,

CE# selects the device and OE# is the output control and should be used to gate data to the output inputs if

the device is selected. Fast page mode accesses are obtained by keeping AmaxâA3 constant and changing

A2âA0 to select the specific word within that page.

Table 7.2 Page Select

Word

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

7.4

Synchronous (Burst) Read Operation

The device is capable of continuous sequential burst operation and linear burst operation of a preset length.

When the device first powers up, it is enabled for asynchronous read operations and can be automatically

enabled for burst mode. To enter into synchronous mode, the configuration register will need to be set.

Prior to entering burst mode, the system should determine how many wait states are desired for the initial

word (tIACC) of each burst access, what mode of burst operation is desired and how the RDY signal will

transition with valid data. The system would then write the configuration register command sequence.

Once the system has written the Set Configuration Register command sequence, the device is enabled for

synchronous reads only.

The data is output tIA after the rising edge of the first CLK. Subsequent words are output tBACC after the

rising edge of each successive clock cycle, which automatically increments the internal address counter.

Note that data is output only at the rising edge of the clock. RDY indicates the initial latency.

7.4.1

Latency Tables for Variable Wait State

The following tables show the latency for variable wait state in a normal Burst operation

Table 7.3 Address Latency for 9 Wait States

Word

Initial Wait

1 ws

9 ws

1 ws

November 8, 2006 S29WS-P_00_A7

S29WS-P

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