SCH3112 Datasheet, PDF (99/396 Pages) SMSC Corporation – LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
LINE STATUS REGISTER (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
Bit 0
Data Ready (DR). It is set to a logic “1” whenever a complete incoming character has been received
and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic “0” by reading
all of the data in the Receive Buffer Register or the FIFO.
Bit 1
Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the
next character was transferred into the register, thereby destroying the previous character. In FIFO
mode, an overrun error will occur only when the FIFO is full and the next character has been
completely received in the shift register, the character in the shift register is overwritten but not
transferred to the FIFO. The OE indicator is set to a logic “1” immediately upon detection of an overrun
condition, and reset whenever the Line Status Register is read.
Bit 2
Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or
odd parity, as selected by the even parity select bit. The PE is set to a logic “1” upon detection of a
parity error and is reset to a logic “0” whenever the Line Status Register is read. In the FIFO mode
this error is associated with the particular character in the FIFO it applies to. This error is indicated
when the associated character is at the top of the FIFO.
Bit 3
Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is
set to a logic “1” whenever the stop bit following the last data bit or parity bit is detected as a zero bit
(Spacing level). The FE is reset to a logic “0” whenever the Line Status Register is read. In the FIFO
mode this error is associated with the particular character in the FIFO it applies to. This error is
indicated when the associated character is at the top of the FIFO. The Serial Port will try to
resynchronize after a framing error. To do this, it assumes that the framing error was due to the next
start bit, so it samples this ‘start’ bit twice and then takes in the ‘data’.
Bit 4
Break Interrupt (BI). Bit 4 is set to a logic “1” whenever the received data input is held in the Spacing
state (logic “0”) for longer than a full word transmission time (that is, the total time of the start bit +
data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status
Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies
to. This error is indicated when the associated character is at the top of the FIFO. When break occurs
only one zero character is loaded into the FIFO. Restarting after a break is received, requires the
serial data (RXD) to be logic “1” for at least ½ bit time.
Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt
whenever any of the corresponding conditions are detected and the interrupt is enabled.
Bit 5
Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a
new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when
the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic “1” when
a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The
bit is reset to logic “0” whenever the CPU loads the Transmitter Holding Register. In the FIFO mode
this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT
FIFO. Bit 5 is a read only bit.
Bit 6
Transmitter Empty (TEMT). Bit 6 is set to a logic “1” whenever the Transmitter Holding Register (THR)
and Transmitter Shift Register (TSR) are both empty. It is reset to logic “0” whenever either the THR
SMSC SCH311X
83
DATASHEET
Rev 0.2 (09-28-04)