SCH3112 Datasheet, PDF (104/396 Pages) SMSC Corporation – LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports

96M
24M
Reg 0xF0
Bit[1]
Mux
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
DIVIDE
BY 12
DIVIDE
BY 13
Reg 0xF0
Bit[0]
MIDI
Sel
Reg 0xF0
Bit[3:2]
Freq
Sel
User
Programmed
Divisor
(16 bit)
Baud
Rate
DIVIDE
BY 6.5
REGISTER BIT
Interrupt Enable Register
Interrupt Identification Reg.
FIFO Control
Line Control Reg.
MODEM Control Reg.
Line Status Reg.
MODEM Status Reg.
INTRPT (RCVR errs)
INTRPT (RCVR Data Ready)
INTRPT (THRE)
RCVR FIFO
XMIT FIFO
PIN SIGNAL
TXDn
nRTSx
nDTRx
Rev 0.2 (09-28-04)
Figure 8.2 Baud Rate Selection
Table 8.5 register Reset
RESET CONTROL
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET/Read LSR
RESET/Read RBR
RESET/Read IIR/Write THR
RESET/
FCR1*FCR0/_FCR0
RESET/
FCR1*FCR0/_FCR0
RESET STATE
All bits low
Bit 0 is high; Bits 1 - 7 low
All bits low
All bits low
All bits low
All bits low except 5, 6 high
Bits 0 - 3 low; Bits 4 - 7 input
Low
Low
Low
All Bits Low
All Bits Low
Table 8.6 Pin Reset
RESET CONTROL
RESET
RESET
RESET
RESET STATE
High-Z (Note 8.3)
High-Z (Note 8.3)
High-Z (Note 8.3)
88
DATASHEET
SMSC SCH311X