LAN9215 Datasheet, PDF (80/134 Pages) SMSC Corporation – Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX

5.3.9
Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
HW_CFG—Hardware Configuration Register
Offset:
74h
Size:
32 bits
BITS
DESCRIPTION
31-25 Reserved
24 AMDIX_EN Strap State. This read-only bit reflects the state of the
AMDIX_EN strap pin (pin 73). This pin can be overridden by PHY Registers
27.15 and 27.13
23-22 Reserved
21
20
16-19
15-14
Transmit Threshold Mode (TTM). This bit is used to control the transmit
threshold the MIL uses as shown in the two tables in the TR field of this
register. This bit is ignored when the SF bit is set (1).
This bit should be set to '1' when operating in 10Mbps mode, and cleared
to '0' when operating in 100Mbps mode if the SF bit cleared.
Store and Forward (SF). When set, this bit instructs the MIL to store a
frame of transmit data in the MIL buffer before forwarding to its final
destination.
If this bit is set, the MIL buffers the entire frame before transmitting. TTM
and TR (see bits 21,13, and 12) are treated as Don’t Cares once the SF
mode is selected.
If this bit is reset, the MAC initiates transmission before it receives the entire
frame from the HBI (Host Bus Interface). TTM and TR (see bit 21,13, and
12) determine when the MIL initiates the transmission. If the host cannot
keep up with the MAC transmitting the Ethernet Packet, there is a risk of an
Underrun Error.
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX Status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See section 5.3.9.1 Allowable settings for
Configurable FIFO Memory Allocationon page 83 for more information.
Reserved
TYPE
RO
RO
RO
R/W
R/W
R/W
RO
DEFAULT
-
AMDIX
Strap
Pin
0
0
5h
-
Revision 1.5 (07-18-06)
80
DATASHEET
SMSC LAN9215