LAN9215 Datasheet, PDF(38/134 Page) SMSC Corporation – Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX

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LAN9215 Datasheet, PDF (38/134 Pages) SMSC Corporation – Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX

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3.11.2.3

Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

Datasheet

Power Management Event Indicators

Figure 3.10 is a simplified block diagram of the logic that controls the external PME, and internal

pme_interrupt signals. The pme_interrupt signal is used to set the PME_INT status bit in the INT_STS

The PME_INT status bit in INT_STS will remain set until the internal pme_interrupt signal is cleared

by clearing the WUPS bits, or by clearing the corresponding WOL_EN or ED_EN bit. After clearing the

internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a â1â to this bit in the

INT_STS register. It should be noted that the LAN9215 can generate a host interrupt regardless of the

state of the PME_EN bit, or the external PME signal.

The external PME signal can be setup for pulsed, or static operation. When the PME_IND bit in the

PMT_CTRL register is set to a â1â, the external PME signal will be driven active for 50ms upon

detection of a wake-up event. When the PME_IND bit is cleared, the PME signal will be driven

continuously upon detection of a wake-up event. The PME signal is deactivated by clearing the WUPS

bits, or by clearing the corresponding WOL_EN or ED_EN bit. The PME signal can also be deactivated

by clearing the PME_EN bit.

WUFR

WUEN

MPR

MPEN

phy_int

WOL_EN

WUPS

ED_EN

WUPS

Other System

Interrupts

PME_INT

Denotes a level-triggered "sticky" status bit

IRQ

PME_INT_EN

IRQ_EN

PME_EN

PME_IND

PME_POL

PME_TYPE

50ms

PME

LOGIC

3.11.3

Figure 3.10 PME and PME_INT Signal Generation

Internal PHY Power-Down modes

There are 2 power-down modes for the internal Phy:

3.11.3.1

General Power-Down

This power-down is controlled by register 0, bit 11. In this mode the internal PHY, except the

management interface, is powered-down and stays in that condition as long as Phy register bit 0.11 is

HIGH. When bit 0.11 is cleared, the PHY powers up and is automatically reset. Please refer to Section

5.5.1, "Basic Control Register," on page 109 for additional information on this register.

Revision 1.5 (07-18-06)

DATASHEET

SMSC LAN9215

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