LAN9215 Datasheet, PDF (123/134 Pages) SMSC Corporation – Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX

Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
6.4
RX Data FIFO Direct PIO Reads
In this mode the upper address inputs are not decoded, and any read of the LAN9215 will read the
RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is
normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9215 . Timing is
identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing
Note: The “Data Bus” width is 16 bits
Table 6.5 RX Data FIFO Direct PIO Read Timing
SYMBOL
t_cycle
t_csl
t_csh
t_csdv
t_asu
t_ah
t_don
t_doff
t_doh
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time (see Note below)
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
MIN
TYP
165
32
13
133
0
0
0
0
MAX
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The
cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order. Parameters t_csh and t_csl must be extended using wait states to meet the
t_cycle minimum.
SMSC LAN9215
123
DATASHEET
Revision 1.5 (07-18-06)