LAN9215 Datasheet, PDF (125/134 Pages) SMSC Corporation – Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX

Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
6.6
PIO Writes
PIO writes are used for all LAN9215 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
A[7:1]
nCS, nRD
Data Bus
Figure 6.5 PIO Write Cycle Timing
Note: The “Data Bus” width is 16 bits.
Table 6.7 PIO Write Cycle Timing
SYMBOL DESCRIPTION
MIN
t_cycle
Write Cycle Time
165
t_csl
nCS, nWR Assertion Time
32
t_csh
nCS, nWR Deassertion Time (see Note below)
13
t_asu
Address Setup to nCS, nWR Assertion
0
t_ah
Address Hold Time
0
t_dsu
Data Setup to nCS, nWR Deassertion
7
t_dh
Data Hold Time
0
TYP
MAX UNITS
ns
ns
133
ns
ns
ns
ns
ns
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Parameters t_csh and t_csl must be extended using wait states to meet the t_cycle minimum.
SMSC LAN9215
125
DATASHEET
Revision 1.5 (07-18-06)