EMC2112 Datasheet, PDF (44/65 Pages) SMSC Corporation – RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

RPM-Based Linear Fan Controller with Hardware Thermal Shutdown
Datasheet
QUEUE[1:0]
1
0
0
1
1
Table 6.16 Fault Queue
0
NUMBER OF CONSECUTIVE OUT OF LIMIT CONDITIONS
0
1 (disabled)
1
2
0
3
1
4 (default)
Bit 1 - 0 - CONV[1:0] - determines the conversion rate of the temperature monitoring. This conversion
rate does not affect the fan driver. The supply current from VDD_3V is nominally dependent upon the
conversion rate and the average current will increase as the conversion rate increases.
CONV[1:0]
1
0
0
0
0
1
1
0
1
1
Table 6.17 Conversion Rate
TEMPERATURE OVER SAMPLING
FROM 11 BITS
CONVERSION RATE
1 / sec
2 / sec
4 / sec (default)
8 / sec
DYN_DIS = ‘0’
x8
x4
x2
x1
DYN_DIS = ‘1’
x1
x1
x1
x1
6.11 Interrupt Status Register
Table 6.18 Interrupt Status Register
ADDR R/W REGISTER B7
B6
B5
B4
Interrupt
23h
R-C
Status
RESET TSD TCRIT
-
Register
B3
B2
B1
B0 DEFAULT
FAN HIGH
-
FAULT
00h
The Interrupt Status Register reports the operating condition of the EMC2112. If any of the bits are set
to a logic ‘1’ (other than RESET and TSD), the ALERT pin will be asserted low if the corresponding
channel is enabled. If there are no set status bits, the ALERT pin will be released.
The bits that cause the ALERT pin to be asserted can be masked based on the channel they are
associated with unless stated otherwise.
Bit 7 - RESET - This bit is set to ‘1’ if the Reset Generator (see Section 5.10) has tripped, meaning
that the VDD_5V voltage level is less than its normal operating level (and the RESET pin is at a logic
‘0’ state). This bit is cleared when the RESET output changes states to a logic ‘1’. This bit will not
cause the ALERT pin to be asserted.
Revision 0.88 (11-20-09)
44
DATASHEET
SMSC EMC2112