SP6120B Datasheet, PDF (9/22 Pages) Sipex Corporation – Low Voltage, AnyFETTM, Synchronous ,Buck Controller Ideal for 2A to 10A, High Performance, DC-DC Power Converters

General Overview: continued
if the conduction current reaches zero and the
Driver Logic has made an attempt to turn the
lower driver on and the Programming Logic is
set for discontinuous mode. Lastly, the 4Ω driv-
ers have internal gate non-overlap circuitry and
are designed to drive MOSFETs associated with
converter designs in the 5A to 10A range. Typi-
cally the high side driver is referenced to the
SWN pin; further improving the efficiency and
performance of the converter.
ENABLE
Low quiescent mode or “Sleep Mode” is initi-
ated by pulling the ENABLE pin below 650mV.
The ENABLE pin has an internal 4µA pull-up
current and does not require any external inter-
face for normal operation. If the ENABLE pin is
driven from a voltage source, the voltage must
be above 1.45V in order to guarantee proper
“awake” operation. Assuming that V_CC is above
2.85V, the SP6120B transitions from “Sleep
Mode” to “Awake Mode” in about 20µs to 30µs
and from “Awake Mode” to “Sleep Mode” in a
few microseconds. SP6120B quiescent current
in sleep mode is 20µA maximum. During Sleep
Mode, the high side and low side MOSFETs are
turned off and the COMP and SS pins are held
low.
Bootstrap Circuit
When SP6120B is programmed to drive a high
side N channel MOSFET, a bootstrap circuit is
required to generate a voltage higher than V_IN to
fully enhance the top MOSFET. A typical boot-
strap only requires a capacitor and diode shown
as C_BST and D_BST in the application circuit on the
front page. When the bottom MOSFET Q_B is
turned on, D_BST is forward biased and charges
the C_BST close to V_IN. When the top MOSFET
turn on, the switch node swings to the V_IN
voltage. Now the voltage at the BST pin is 2*V_IN
and D_BST is reverse biased. The BST pin voltage
powers the high side MOSFET driver, and thus
the GH output goes up to 2*V_IN to provide a V_DS
equal to V_IN.
Under certain conditions, the bottom MOSFET
may not turn on long enough to replenish C_BST
voltage. Therefore, when the top MOSFET turns
on, the BST pin may not be high enough to fully
enhance the switch. To prevent this operation,
SP6120B monitors the BST pin voltage in refer-
ence to the V_CC voltage. When the BST pin
voltage is less than V_BST OK threshold, the
controller forces the GL to turn on for MINI-
MUM GL ON at the end of the switching cycle.
This provides enough time to recharge the C_BST
and ensures the proper operation of the boot-
strap circuit.
UVLO
Assuming that the ENABLE pin is either pulled
high or floating, the voltage on the V_CC pin then
determines operation of the SP6120B. As V_CC
rises, the UVLO block monitors V_CC and keeps
the high side and low side MOSFETs off and the
COMP and SS pins low until V_CC reaches 2.85V.
If no faults are present, the SP6120B will initiate
a soft start when V_CC exceeds 2.85V. Hysteresis
(about 100mV) in the UVLO comparator pro-
vides noise immunity at start-up.
Soft Start
(see figures on next page)
Soft start is required on step-down controllers to
prevent excess inrush current through the power
train during start-up. Typically this is managed
by sourcing a controlled current into a program-
ming capacitor (on the SS pin) and then using the
voltage across this capacitor to slowly ramp up
either the error amp reference or the error amp
output (COMP). The control loop creates nar-
row width driver pulses while the output voltage
is low and allows these pulses to increase to their
steady-state duty cycle as the output voltage
increases to its regulated value. As a result of
controlling the inductor volt*second product
during start-up, inrush current is also controlled.
The presence of the output capacitor creates
extra current draw during start-up. Simply stated,
dV_OUT/dt requires an average sustained current
in the output capacitor and this current must be
considered while calculating peak inrush current
and over current thresholds. Since the SP6120B
ramps up the error amp reference voltage, an
expression for the output capacitor current can
be written as:
IC_OUT = (C_OUT/C_SS) * (V_OUT/1.25) * 50µA
Date: 5/25/04
SP6120B Low Voltage, AnyFET^TM, Synchronous, Buck Controller
9
© Copyright 2004 Sipex Corporation