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SP6120B Datasheet, PDF (12/22 Pages) Sipex Corporation – Low Voltage, AnyFETTM, Synchronous ,Buck Controller Ideal for 2A to 10A, High Performance, DC-DC Power Converters
Program Logic: continued
PROGRAM LOGIC TRUTH TABLE
PROGRAM PIN
NFET OR PFET
MODE
Short to GND
NFET
Continuous
68 kΩ to GND
NFET
Discontinuous
Short to VCC
68 kΩ to VCC
PFET
PFET
Continuous
Discontinous
The NFET/PFET programmability is for the
high side MOSFET. When designing DC/DC
converters, it is not always obvious when to use
an NFET with a charge pump or a simple PFET
for the high side MOSFET. Often, the controller
has to be changed, making performance evalua-
tions difficult. This difficulty is worsened by the
limited availability of true low voltage control-
lers. In addition, by also programming the mode,
continuous or discontinuous, switch mode power
designs that are successful in bus applications
can now find homes in portable applications.
Secondary Loop (3% Window Comparator)
DSP, microcontroller and microprocessor appli-
cations have very strict supply voltage require-
ments. In addition, the current requirements to
these devices can change drastically. Linear
regulators, typically the workhorse for DC/DC
step-down, do a great job managing accuracy
and transient response at the expense of effi-
ciency. On the other hand, PWM switching
regulators typically do a great job managing
efficiency at the expense of output ripple and
line/load step response. The trick in PWM
controller design is to emulate the transient re-
sponse of the linear regulator.
Of course improving transient response should
be transparent to the power supply designer.
Very often this is not the case. Usually the very
circuitry that improves the controllers transient
response adversely interferes with the main PWM
loop or complicates the board level design of the
power converter.
The SP6120B handles line/load transient re-
sponse in a new way. First, a window compara-
tor detects whether the output voltage is above
or below the regulated value by 3%. Then, a
proprietary “Ripple & Frequency Independent”
algorithm synchronizes the output of the win-
dow comparator with the peak and valley of the
inductor current waveform. 3% low detection is
synchronized with inductor current peak; 3%
high detection is synchronized with the inductor
current valley. However, in order to eliminate
any additional loops, the current peak and valley
are determined by the edges associated with the
on-time in the main loop. The set pulse corre-
sponding to the start of an on-time indicates a
MAX
DC Load
Current
MIN
0A
Output
Voltage
VOUT
Reset
Main Loop
Set
V(VCC)
3% High
Latch On
0V
V(VCC)
3% Low
Latch On
0V
.
TIME
Date: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
12
© Copyright 2004 Sipex Corporation