SP6120B Datasheet, PDF (16/22 Pages) Sipex Corporation – Low Voltage, AnyFETTM, Synchronous ,Buck Controller Ideal for 2A to 10A, High Performance, DC-DC Power Converters

are prone to such surge current when power
supplies are connected ‘live’ to low impedance
power sources. Certain tantalum capacitors, such
as AVX TPS series, are surge tested. For ge-
neric tantalum capacitors, use 2:1 voltage derat-
ing to protect the input capacitors from surge
fall-out.
MOSFET Selection
The losses associated with MOSFETs can be
divided into conduction and switching losses.
Conduction losses are related to the on resis-
tance of MOSFETs, and increase with the load
current. Switching losses occur on each on/off
transition when the MOSFETs experience both
high current and voltage. Since the bottom
MOSFET switches current from/to a paralleled
diode (either its own body diode or a Schottky
diode), the voltage across the MOSFET is no
more than 1V during switching transition. As a
result, its switching losses are negligible. The
switching losses are difficult to quantify due to
all the variables affecting turn on/off time. How-
ever, the following equation provides an ap-
proximation on the switching losses associated
with the top MOSFET driven by SP6120B.
P_{SH (max)} = 12C _rssV _{IN (max)}I _{OUT (max)}F_S
where
C_rss = reverse transfer capacitance of the top
MOSFET
Switching losses need to be taken into account
for high switching frequency, since they are
directly proportional to switching frequency.
The conduction losses associated with top and
bottom MOSFETs are determined by:
P = R I D _{CH (max)}
2
DS (ON ) OUT (max)
P_CL(max) = R _{DS(ON )}I _{OUT (max)2}(1 − D)
where
P_CH(max) = conduction losses of the high side
MOSFET
P_CL(max) = conduction losses of the low side
MOSFET
R_DS(ON) = drain to source on resistance.
The total power losses of the top MOSFET are
the sum of switching and conduction losses. For
synchronous buck converters of efficiency over
90%, allow no more than 4% power losses for
high or low side MOSFETs. For input voltages
of 3.3V and 5V, conduction losses often domi-
nate switching losses. Therefore, lowering the
R_DS(ON) of the MOSFETs always improves
efficiency even though it gives rise to higher
switching losses due to increased C_rss.
Top and bottom MOSFETs experience unequal
conduction losses if their on time is unequal. For
applications running at large or small duty cycle,
it makes sense to use different top and bottom
MOSFETs. Alternatively, parallel multiple
MOSFETs to conduct large duty factor.
R_DS(ON) varies greatly with the gate driver volt-
age. The MOSFET vendors often specify R_DS(ON)
on multiple gate to source voltages (V_GS), as
well as provide typical curve of R_DS(ON) versus
V_GS. For 5V input, use the R_DS(ON) specified at
4.5V V_GS. At the time of this publication, ven-
dors, such as Fairchild, Siliconix and Interna-
tional Rectifier, have started to specify R_DS(ON)
at V_GS less than 3V. This has provided necessary
data for designs in which these MOSFETs are
driven with 3.3V and made it possible to use
SP6120B in 3.3V only applications.
Thermal calculation must be conducted to en-
sure the MOSFET can handle the maximum
load current. The junction temperature of the
MOSFET, determined as follows, must stay
below the maximum rating.
T = T + ^P _{R J (max)}
A (max)
MOSFET (max)
θ JA
where
T_A(max) = maximum ambient temperature
PMOSFET(max) = maximum power dissipa-
tion of the MOSFET
R_ΘJA = junction to ambient thermal resistance.
R_ΘJA of the device depends greatly on the board
layout, as well as device package. Significant
thermal improvement can be achieved in the
maximum power dissipation through the proper
design of copper mounting pads on the circuit
board. For example, in a SO-8 package, placing
Date: 5/25/04
SP6120B Low Voltage, AnyFET^TM, Synchronous, Buck Controller
16
© Copyright 2004 Sipex Corporation